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Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

Easy interface to all microprocessors, or operates “stand alone”. Differential analog voltage inputs.

No zero adjust required. Operates ratiometrically or with 5 V. Error Specification Includes Full-Scale. Zero Error, and Non-Linearity.

At Other Input and Outputs. Vapor Phase 60 seconds. Package Dissipation at T. ESD Susceptibility Note The following specifications apply for V. Total Adjusted Error Note 8. Total Unadjusted Error Note fatasheet.

Analog Input Voltage Range. Over Analog Input Voltage. Voltage Range Note 4. Conversion Rate in Free-Running. Access Time Delay from Falling. Delay from Falling Edge. Input Capacitance of Logic.

ADC Datasheet PDF – Texas Instruments

eatasheet Logical “1” Input Voltage. Logical “0” Input Voltage. Logical “1” Input Current. Logical “0” Input Current. Logical “0” Output Voltage. Logical “1” Output Voltage. Leakage All Data Buffers. Short to Gnd, T. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd. A zener diode exists, internally, from V. Two on-chip diodes are tied to each analog input see block diagram which will forward conduct.


Be careful, during testing at low V. The spec allows 50 mV forward bias of either diode. This means that adtasheet long as the analog V. To achieve an absolute 0 V. Accuracy is guaranteed at f. At higher clock frequencies accuracy can degrade. For lower clock xdc0801, the duty cycle limits can be.

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Datashete an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see.

An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low datawheet high transition of the WR pulse see timing diagrams. To obtain zero code at other analog input voltages see section 2. Human body model, pF discharged through a 1. Logic Input Threshold Voltage vs.

8-Bit ┬ÁP Compatible A/D Converters

Full-Scale Error vs Conversion Time. Effect of Unadjusted Offset Error vs. Output Current vs Temperature.

Power Supply Current vs Temperature Note 9. Linearity Error at Low V. Ratiometeric with Full-Scale Adjust. Absolute with a 2. Absolute with a 5V Reference.

Zero-Shift and Span Adjust: Directly Converting a Low-Level Signal. Digitizing a Current Flow. Self-Clocking in Free-Running Dataasheet. Operating with “Automotive” Ratiometric Transducers. Omit circuitry within the dotted area if adc8001 is not needed. Analog Self-Test for a System. Noise Filtering the Analog Input. Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order, low-pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used.

The horizontal scale is analog input. LSB away from each center-value. As shown, the risers. Correct digital output codes will be provided for a range of analog input voltages that extend.

Sampling an AC Input Signal. Oversample whenever possible [keep fs. Consider the amplitude errors which are introduced within the passband of the filter. Logic inputs can be driven to V. LSB from the ideal center-values. Each tread the range. Figure 2 shows a worst case error plot for the ADC All center-valued inputs are guaranteed to produce dqtasheet correct acd0801 codes and the adjacent risers are guaranteed to be no closer to the center-value points than.


The maximum range of the position of the code transition is indicated by the horizontal arrow and it is addc0801 anteed to be no more than. The error curve of.

Figure 3 shows a worst case error plot for. Next to each transfer function is shown the corresponding error plot. Many people may be more familiar with error plots than transfer functions. For example the error at point 1 of. LSB because the digital code appeared. The error plots always have a constant negative slope and the abrupt up- side steps are always 1 LSB in magnitude. The ADC series contains a circuit equivalent of the R network.

Analog switches are sequenced by succes- sive approximation logic to match the analog difference input voltage [V. A conversion in process can be interrupted by issuing a second start command. To ensure start-up under all possible conditions, an external WR pulse is required during the first power-up cycle. Datazheet the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset. Conversion will start from 1 to 8 clock.

All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines. The converter is started by having CS and WR simulta- neously low. An inverting buffer then supplies the INTR input signal. This reduces the width of the resulting INTR output pulse to only a few propagation delays approximately ns.

L logic voltage levels. These signals have been renamed. In dstasheet, these inputs are active low to allow an easy interface to microprocessor control busses.